1. Field of the Invention
The present invention relates to a data processing system, and more particularly, the present invention relates to a data processing system for the interrupt latency of the microprocessor.
2. Description of the Prior Art
In the microprocessor used in common electronic, non-personal computer, devices such as a digital camera, the interrupt vector table of the data processing system comprises a set of vector addresses; each address stores an entry instruction of the interrupt service routine (The entry instruction is the first instruction of the whole interrupt service routine). When the central processing unit (CPU) accepts an interrupt request, the CPU reads the interrupt vector table and executes the interrupt service routine corresponded to the interrupt request.
In this type of data processing system, because the address of the reset vector is next to the other vectors, when booting the microprocessor, the CPU fetches the first program instruction of the whole application program in the reset vector to execute; therefore, the reset vector must be located in the non-volatile memory, such as the erasable programmable read-only memory (EPROM) or the flash read-only memory (Flash ROM) . . . etc.
However, when the CPU reads the non-volatile memory, the reading speed is slow; therefore, in real practice, the whole application program, comprised of the interrupt service routines, will be copied into the higher speed volatile memory to be executed by the CPU for increasing the executing efficiency.
Referring to FIG. 1, FIG. 1 is a function block diagram of a conventional data processing system 1. The data processing system 1 comprises a set of memory modules 30 for storing program instructions and data, a microprocessor 20, a power source 28, and a bus 60.
The memory modules 30 comprise a low-speed memory 32 and a high-speed memory 34. The low-speed memory 32 stores an interrupt vector table 36 for recording at least one entry instruction of an interrupt service routine.
The power source 28 is used for providing electrical power to the data processing system 1. The power source 28 comprises a switch 29. When the power source 28 is shut down, the program instructions and data stored in the high-speed memory 34 are lost; however,-the program instructions and data stored in the low-speed memory are preserved.
The microprocessor 20 comprises a CPU 22 for executing program instructions and calculating data. The CPU 22 is designed to fetch program instructions in the low-speed memory 32 when an interruption occurs.
The bus 60 is used for connecting to the CPU 22 and the memory modules 30 for transmitting program instructions and data.
When an interruption occurs, the CPU 22 fetches the corresponding entry instruction of the interrupt service routine in the interrupt vector table 36 of the low-speed memory 32.
By the restriction of the basic architecture of the CPU, when an interruption occurs, the CPU fetches the entry instruction of the interrupt service routine in the low-speed non-volatile memory, and thenbranches to the rest of program located in the high speed memory. Although this method is commonly used, the interrupt service efficiency of the CPU is restricted. If the interrupt latency can be reduced, the system executing efficiency can be improved.